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An FPGA based generic framework for high speed sum of absolute difference implementation

journal contribution
posted on 2023-06-07, 23:20 authored by Saad Rehman, Rupert YoungRupert Young, Chris ChatwinChris Chatwin, Phil BirchPhil Birch
In this paper we present a hardware architecture for the Sum of Absolute Difference (SAD) technique. This paper also gives the design details and the implementation results for an FPGA based core that permits realisation of a high speed matching algorithm for real time image processing applications. The matching criterion chosen is the SAD algorithm The implementation provides the correct position of the target within the frame/image. The ease of implementation lies in the fact that the core is highly parameterized and therefore can cater effectively to the needs of different sizes and resolutions of images and filters. The high speed and the low area of silicon usage make it useful for a number of image processing applications. The paper also gives a review of different hardware architectures. © EuroJournals Publishing, Inc. 2009.

History

Publication status

  • Published

Journal

European Journal of Scientific Research

ISSN

1450-216X

Issue

1

Volume

33

Page range

6-29

Pages

25.0

Department affiliated with

  • Engineering and Design Publications

Full text available

  • No

Peer reviewed?

  • Yes

Legacy Posted Date

2012-02-06

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